In the present era of very large scale integration (VLSI), in which the dimensions of transistors and other semiconductor structures are shrinking below one micrometer, a host of new problems must be addressed. In general, greater isolation is required between devices. For CMOS applications, this isolation must prevent latch-up. At the same time, this increased isolation must not be provided at the expense of available chip space.
Silicon-on-insulator technology appears to be a particularly promising method of addressing this problem. A general example of this technology is shown in the article by R. J. Lineback, "Buried Oxide Marks Route to SOI Chips", Electronics Week, Oct. 1, 1984, pp. 11-12. As shown in this article, oxygen ions are implanted into a bulk silicon to form a buried oxide layer therein. The implant is then annealled for two hours so that the portion of the silicon lying above the buried oxide is single-crystal silicon. The various semiconductor devices are then formed on the single-crystal layer. The underlying buried oxide provides isolation between adjacent devices.
More recently, a specific method of forming silicon-on-insulator structures has evolved, in which two silicon substrates are bonded together and one of the substrates is at least partially removed. An example of this method is disclosed in an article by M. Kimura et al, "Epitaxial Film Transfer Technique for Producing Single Crystal Si Film on an Insulating Substrate", Applied Physics Letters, Vol. 43, No. 3, Aug. 1, 1983. As described in this article, a first p+ substrate has a P- epitaxial layer grown thereon. A second substrate has a layer of oxide grown thereon. Both substrates are then coated with a glass, and the two substrates are bonded together using these glass layers. More specifically, the glass layers of the two substrates are pressed together and are heated to about 930.degree. C. After the substrates are bonded together, the substrate having the epitaxial layer is removed, leaving behind the epitaxial layer on the bonded glass layers. The glass layers provide insulation. See also the article by Brock et al, "Fusing of Silicon Wafers", IBM Technical Disclosure Bulletin, Vol. 19, No. 9, February 1977, pp. 3405-3406, in which it is stated that "wafers may be fused together conveniently by forming a layer of silicon dioxide on each wafer, then placing the layers of silicon dioxide abutting each other, and heating, preferably in a steam atmosphere at a temperature in the order of 1050.degree. C. for about one-half hour."
U.S. Pat. No. 4,142,925 (issued 3/3/79 to King et al) discloses a method of making a structure which includes an epitaxial layer, an insulator layer and a polished silicon layer. As shown in the front figure of the patent, an epitaxial layer is grown on an n+ silicon substrate. An insulator layer of SiO.sub.2 is grown on the epitaxial layer, and the insulator is covered with a polysilicon support layer. The n+ silicon substrate is then removed, leaving the epitaxial layer atop the SiO.sub.2 layer.
It has been found that the step of removing the silicon substrate without removing the underlaying epitaxial layer is facilitated if these two layers have different doping concentrations or are of different conductivity types. For example, if the substrate is p+ and the epitaxial layer is p- or n type, the substrate may be removed by etching in a 1:3:8 solution of hydroflouric, nitric and acetic ("HNA") acid.
A problem with the above process is that the HNA acid will etch to the p+/p- or p+/n junction, which does not occur at the actual physical interface of these two layers. For example, in order to form a final n epitaxial layer of 200 nm (nanometers) on a p+ substrate, an epitaxial layer of 1000-1200 nm must be deposited. This is because boron will out-diffuse from the substrate into the epitaxial layer, such that the p+/n junction actually occurs at a point approximately 800-1000 nm, respectively, above the physical interface between the substrate and the epitaxial layer.
Forming a 1000-1200 nm layer of epitaxy leads to another problem. Typically, when working in the nm range, the deposition tools used in the industry can deposit a layer with approximately plus or minus 5 percent error. Thus, if the original epitaxial layer is 1000 nm thick, the final epitaxial layer (i.e. after removal of the p+ substrate) will be approximately 250.+-.50 nm thick. When the dopant concentration of the epitaxial layer is sufficiently low, the depletion regions of the channels of FETs subsequently formed on the epitaxial layer will extend to the bottom of the layer. Hence, the threshold voltages of these FETs are at least partially determined by the thickness of the epitaxial layer, such that the above variation in thickness would lead to an unacceptable variation in the threshold voltages of the FETs. Obviously, as the thickness of the epitaxial layer as initially deposited is increased, the resultant thickness variation increases. For example, if the initial epitaxial thickness is 2500 nm, its final thickness would be approximately 250.+-.150 nm.